1. Field of the Invention
This invention relates in general to digital signal processing, and more particularly to a method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations.
2. Description of Related Art
Techniques are known in the domain of integrated circuits using calculation units for verifying if the format allowed for the result of an arithmetic operation carried out by an AU (Arithmetic Unit) on two operands and an input carry digit does not exceed a given format. This technique has applications in most calculation units, such as, calculation units included in programmable circuits, such as, a digital signal processor (DSP) or a microcontroller.
To process the applications, the central processing unit includes circuitry to receive and decode instructions and circuitry to process data in accordance with the decoded instructions. The circuitry to process the data typically includes an arithmetic logic unit (ALU). The arithmetic logic unit performs arithmetic functions such as add, subtract, multiply, divide, shift data, etc. and performs logic functions such as AND, OR, NAND, NOR, exclusive OR, etc. More specifically, the ALU consists of two kinds of operations: arithmetic operation such as addition/subtraction and logical operation.
Addition and subtraction are straightforward and unexceptional. When adding two i-bit numbers, the result may be an n+1-bit binary due to the carry-out. In computer hardware, data is typically represented as fixed-width number. Thus, the sum of 0110 and 1110 will be 0100 in a 4-bit processor and an overflow is used to point out the result is erroneous. Subtraction behaves similar. The same problem occurs in two's complement number system, under different condition. In the twos complement representation, negative numbers are represented as the result of a subtraction of the magnitude of the number from zero. That is, in a four-bit system, for example, a negative 2 is represented as the result of 0000 minus 0010, which is 1110 (the borrow, or carry, produced by the subtraction is ignored). The twos complement representation has the advantageous characteristic that additions and subtractions of twos complement numbers can be effected without regard for whether the numbers being added or subtracted are positive or negative. In the two's complement number system, the overflow occurs when adding two positive numbers and the sum is negative, or vice versa. Clearly, adding or subtracting two 32-bit numbers can yield a result that needs 33-bits to be fully expressed. The lack of a 33rd bit means that the overflow occurs and the sign bit is being set with the value of the result instead of the proper sign of the result.
Multiplication of signed numbers requires special care. For example, multiplying numbers with the same sign produces a positive product, but multiplying a positive number by a negative number yields a negative product. Multiplication may be performed using a sequence of shifts and additions. To achieve the data shift function, the arithmetic logic unit includes an arithmetic shifter. An arithmetic shifter is used to store a bit-vector of some specified length. It has two control signals: shift-left and shift-right. When shift-left is asserted, the bits in the vector are shifted one bit to the left, with a 0 shifted into the rightmost bit. When shift-right is asserted, the bits in the vector are shifted one bit to the right, with a copy of the most significant bit shifted into the leftmost bit.
An arithmetic shifter is typically implemented using a shift register. A shift register is a group of registers set up in a linear fashion that have their inputs and outputs connected together in such a way that the data is shifted down the line when the circuit is activated. Shifting a word right or left (which is equivalent to multiplying or dividing by a power of 2) is used in multiplication and division and also to align data on byte or word boundaries.
ALU results are saturated upon overflow. Arithmetic overflow is the condition that occurs when a calculation produces a result that is greater than a given register or storage location can store or represent. A digital processor may use a self-saturating number representation in which any arithmetic operation which generates an overflow will automatically set the output to a value having the proper sign and a magnitude equal to the maximum value which can be represented by the digital data word. For example, ALU saturation logic may be used to prevent a result from overflowing by keeping the result at a maximum (or minimum) value. Thus, when arithmetic operations produce values too large or too small for registers, the largest or smallest value that can be represented is substituted instead. More specifically:                if ((result=a±b)>(2n-1))                    result=2n-1;                        else if ((a±b)<=−2n)                    result=−2n;However, there is typically no solution for saturating the result of 2x*data. Furthermore, solutions that are used are very expensive in terms of cycles.                        
It can be seen then that there is a need for a method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations.